1. Field of the Invention
The present invention relates to packaging assembly packaging technology, more specifically to a wiring board and a packaging assembly using the same for a BGA.
2. Description of the Related Art
According to the progress of high integration of semiconductor chips, demand for high-density mounting technique for packaging assemblies has increased. As a semiconductor package with increased density, dual in-line package (DIP), quad flat package (QFP), small out-line package (SOP), small out-line j-leaded package (SOJ), and the like are known. In the above semiconductor packages, reduction of a terminal pitch, surface mounting, and multi-terminal area are enabled. Recently, a multi-terminal ball grid array (BGA) package which can be surface-mounted at high density has been actively developed. In a wiring board of the semiconductor package, when frequency is increased due to the enhancement of an operating speed, power supply noise, cross talk noise or the like is generated. Especially, in a LSI chip which operates at the frequency of several hundred MHz and performs computation, development and practical use of the device which can suppress the occurrence of crosstalk noise occurring between signal wiring as much as possible is expected. As a method of shielding such noises, arranging a high voltage power distribution layer (VDD layer) or a low voltage power distribution layer (GND layer) between signal wirings is proposed.
A packaging assembly 100 shown in FIG. 1 is an example of the semiconductor package used for a high speed static random access memory (SRAM) The packaging assembly 100 includes a multilayered substrate 101, a semiconductor chip 103 mounted on the multilayered substrate 101, and solder balls 104a, 104b, . . . , and 104f arranged underneath the multilayered substrate 101. The multilayered substrate 101 further includes metal traces 113a and 113b, insulating boards 110a, 110b and 110c, a VDD layer 114, a GND layer 115, and lands 116a, 116b, . . . , and 116f. The metal traces 113a and 113b are arranged on the top surface of insulating board 110a. The VDD layer 114 is stretched over the entire surface between the insulating board 110a and the insulating board 110b. The GND layer 115 is stretched over the entire surface between the insulating board 110b and the insulating board 110c. The lands 116a, 116b, . . . , and 116f are arranged under the insulating board 110c. On the inside the multilayered substrate 101, through holes and via holes (not shown) are arranged, and metal traces 113a and 113b on the side of the chip are electrically connected in three-dimensional directions. In this way, as for the packaging assembly 100, the metal traces 113a and 113b and the lands 116a, 116b, . . . , and 116f are arranged through the VDD layer 114 and the GND layer 115, which are metallic layers disposed over the entire surface between the insulating boards 110a, 110b, and 110c. Thus, the generation of noises can be shielded in three-dimensional directions.
A packaging assembly 200 shown in FIG. 2 is an example of the semiconductor package used for rambus dynamic random access memory (RDRAM). The packaging assembly 200 includes a left-side wiring board 201a, a right-side wiring board 201b arranged on the same plane with the left-side wiring board 201a in such a manner that a space is formed therebetween. The packaging assembly 200 further includes a semiconductor chip 203 which is mounted facedown to the upper part of the left-side wiring board 201a and the right-side wiring board 201b. Bonding pads 206 are arranged underneath the semiconductor chip between the left-side wiring board 201a and the right-side wiring board 201b. Solder balls 204a, 204b, . . . , and 204d are disposed underneath the wiring boards 201a and 201b. The left-side wiring board 201a includes an insulating board 210a and a wiring layer 211a disposed underneath the insulating board 210a. The wiring layer 211a includes lands 216a and 216b, a VDD wiring 215, and a signal wiring 213a. The lands 216a and 216b are disposed like a matrix underneath the insulating board 210a, the VDD wiring 215 is arranged surrounding the circumference of the lands 216a and 216b in parallel directions, and the signal wiring 213a is separately arranged from the lands 216a and 216b through the VDD wiring 215. The right-side wiring board 201b includes an insulating board 210b and a wiring layer 211b arranged underneath the insulating board 210b. The wiring layer 211b includes lands 216c and 216d, a GND wiring 214, and a signal wiring 213b. The land 216c is disposed underneath the insulating board 210b, the GND wiring 214 is arranged separately from the lands 216c and 216d surrounding the circumference of the lands 216c and 216d in parallel directions, and the signal wiring 213b is separately arranged from the lands 216c and 216d through the GND wiring 214. The signal wirings 213a and 213b are connected to the semiconductor chip 203 through bonding wires 205 and bonding pads 206. In the packaging assembly 200 forming the above-described structure, the signal wirings 213a and 213b and the GND wiring 214 or the VDD wiring 215 are arranged around the circumference of the lands 216c and 216d. Thus, the generation of noises can be shielded in two-dimensional directions.
However, in the packaging assembly 100 shown in FIG. 1, the leakage of the electromagnetic field, which is the cause of noise generation, can be shielded in three-dimensional directions. In addition, a plurality of dielectric layers and a plurality of metallic interconnection layers are required to for the multilayered substrate, in which the dielectric layers and the metallic interconnection layers are alternately laminated. Therefore, the entire body of the device becomes thick, involving a cost increase. Also, since the packaging assembly 200 shown in FIG. 2 has electric lines of force with large leakage, the effect of shielding the electromagnetic field is reduced compared with the multilayered substrate 101 shown in FIG. 1.